555 Timer Calculator
Frequency, duty cycle, and pulse width for a 555 from its resistors and capacitor.
Period 1.46 ms — high for 762 µs, low for 693 µs.
Always above 50% in this configuration, because the capacitor charges through R1 + R2 but discharges through R2 alone. Making R1 much smaller than R2 pushes it towards 50%.
Timing is set by R and C only — supply voltage does not appear in the formula, which is why a 555 holds its frequency as a battery drains. Datasheets quote the astable constant as 1.44; that is 1/ln2 rounded, and this calculator uses the exact value.
In astable mode the 555 oscillates at f = 1 ÷ (ln2 × (R1 + 2R2) × C). With R1 = 1 kΩ, R2 = 10 kΩ, and C = 100 nF that gives about 687 Hz at a 52% duty cycle. In monostable mode one trigger gives a pulse of 1.1 × R × C.
One chip, two useful behaviours
The 555 has been in production since 1972 and is still the default answer for "I need something to blink, beep, or wait." Its two standard configurations do almost everything hobby circuits ask of a timer.
Astable mode makes it a free-running oscillator: the capacitor charges through R1 and R2, discharges through R2 alone, and the output flips between high and low forever. Monostable mode makes it a one-shot: it sits low until triggered, then holds the output high for a fixed time and returns.
Why the duty cycle is never below 50%
The asymmetry is built into the circuit. Charging current flows through R1 + R2, but discharging happens through R2 only, so the high time is always longer than the low time. As R1 shrinks relative to R2 the duty cycle approaches 50%, but it cannot reach or pass it in the basic configuration.
Getting below 50% needs a diode across R2 so charging bypasses it — a standard modification, but not what the plain formula describes.
ln2 ≈ 0.693. Datasheets usually quote the astable constant as 1.44, which is 1/ln2 rounded; this calculator uses the exact value, so it reads about 0.2% higher.
Worked example: 1 kΩ, 10 kΩ, 100 nF
Charge time, discharge time, then the frequency:
- 1 Find the high time. ln2 × (1 kΩ + 10 kΩ) × 100 nF = 0.693 × 11,000 × 1e−7 = 0.762 ms.
- 2 Find the low time. ln2 × 10 kΩ × 100 nF = 0.693 ms — shorter, because discharge skips R1.
- 3 Add them for the period. 0.762 + 0.693 = 1.456 ms.
- 4 Invert for frequency. 1 ÷ 0.001456 s ≈ 687 Hz.
- 5 Work out the duty cycle. (R1 + R2) ÷ (R1 + 2R2) = 11,000 ÷ 21,000 = 52.4% high.
- 6 Check the supply is irrelevant. No voltage term appears — the frequency holds as a battery drains, which is the chip’s main virtue.
Common astable values with C = 100 nF
Frequency and duty cycle for a few R1/R2 pairs. Larger resistors and capacitors both slow the oscillator.
| R1 | R2 | Frequency | Duty cycle |
|---|---|---|---|
| 1 kΩ | 1 kΩ | 4.81 kHz | 66.7% |
| 1 kΩ | 10 kΩ | 687 Hz | 52.4% |
| 10 kΩ | 10 kΩ | 481 Hz | 66.7% |
| 1 kΩ | 100 kΩ | 71.8 Hz | 50.2% |
| 10 kΩ | 100 kΩ | 68.7 Hz | 52.4% |
| 100 kΩ | 100 kΩ | 48.1 Hz | 66.7% |
Practical limits
The formulas are exact for an ideal chip, but a real 555 has boundaries. Very large timing resistors — above roughly 1 MΩ — make the circuit sensitive to the chip's own leakage current, and timing drifts. Very small ones waste current and can exceed the discharge transistor's rating; staying above about 1 kΩ is the usual advice.
At the other end, the classic bipolar 555 becomes unreliable above a few hundred kilohertz because its internal switching is not fast enough. CMOS versions such as the 7555 run faster, draw far less current, and work at lower supply voltages — worth knowing when a design has to run from a coin cell.
One more practical note that costs people hours: the 555 draws a sharp current spike each time its output switches, which can upset the rest of a circuit. A 100 nF decoupling capacitor directly across the chip's supply pins is not optional in a real build, even though it does not appear anywhere in the timing arithmetic.